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Select and reserve the inter-MSC circuit that will provide the landline connection between the serving MSC and the target MSC Request a call handoff to the target MSC The serving MSC uses the FacilitiesDirective Invoke (FACDIR) message7 for this purpose When notified that the target MSC accepts the call handoff request via the FacilitiesDirective Return Result (facdir) message, direct the MS to move from the current serving radio channel to the desired target radio channel When notified that the MS has moved to the target channel via the MobileOnChannel Invoke (MSONCH) message, connect the other party to the MS by using the inter-MSC circuit If the handoff occurs while the MS is awaiting answer (ie, in the case of an MS-originated call), wait until the called party answers and then inform the target MSC, using the InterSystemAnswer Invoke (ISANSWER) message (see Figure 97)

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pins have 1 unit of loading capacitance to the driver driving them The intrinsic rise and fall delays listed with pin o1 specify the delay to the output with no loading The timing analyzer uses the intrinsic delays plus the rise and fall resistance with the output loading to calculate the delay through a particular gate Notice that the function of pin o1 is listed as the AND of pins a1 and a2 Also, notice that pin o1 is related to pins a1 and a2 in that the timing delay through the device is calculated from pins a1 and a2 to pin o1 Most synthesis tools have fairly complicated delay models to calculate timing through an ASIC cell These models include not only intrinsic rise and fall time, but output loading, input slope delay, and estimated wire delay A diagram illustrating this is shown in Figure 9-7 The total delay from gate A1 to gate C1 is:

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Unless otherwise indicated, the FacilitiesDirective2 operation may be substituted for references to the FacilitiesDirective operation; eg, either FacilitiesDirective Invoke or FacilitiesDirective2 Invoke messages may be used by the serving MSC The FacilitiesDirective2 operation was added to IS-41 in Revision C to support all air-interface standards, including CDMA and narrowband AMPS (NAMPS) MSs; the FacilitiesDirective operation supports TDMA and AMPS MSs, but not CDMA or NAMPS

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Downloaded from Digital Engineering Library @ McGraw-Hill (wwwdigitalengineeringlibrarycom) Copyright 2004 The McGraw-Hill Companies All rights reserved Any use is subject to the Terms of Use as given at the website

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next_state <= bgtI3; when bgtI3 => opRegRd <= 1 ; regSel <= instrReg(2 downto 0); regRd <= 1 ; compsel <= gt; next_state <= bgtI4; when bgtI4 => opRegRd <= 1 after 1 ns; regSel <= instrReg(2 downto 0); regRd <= 1 ; compsel <= gt; if compout = 1 then next_state <= bgtI5; else next_state <= incPc; end if; when bgtI5 => progcntrRd <= 1 ; alusel <= inc; shiftSel <= shftpass; next_state <= bgtI6; when bgtI6 => progcntrRd <= 1 ; alusel <= inc; shiftsel <= shftpass; outregWr <= 1 ; next_state <= bgtI7; when bgtI7 => outregRd <= 1 ; next_state <= bgtI8; when bgtI8 => outregRd <= 1 ; progcntrWr <= 1 ; addrregWr <= 1 ; next_state <= bgtI9; when bgtI9 => vma <= 1 ; rw <= 0 ; next_state <= bgtI10; when bgtI10 => vma <= 1 ; rw <= 0 ; if ready = 1 then progcntrWr <= 1 ;

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Figure 96 An example of the handoff-forward processes: (1) The serving MSC requests a handoff forward (2) The target MSC accepts the handoff request (3) The selected inter-MSC circuit is now ready for the handoff (4) The serving MSC issues a handoff order to the MS (5) The MS tunes to the new channel and is detected by the target MSC (6) The target MSC notifies the serving MSC that the MS has been detected (7) The serving MSC connects the call path to the inter-MSC circuit, completing the handoff

next_state <= loadPc; else next_state <= bgtI10; end if; when inc2 => regSel <= instrReg(2 downto 0); regRd <= 1 ; alusel <= inc; shiftsel <= shftpass; outregWr <= 1 ; next_state <= inc3; when inc3 => outregRd <= 1 ; next_state <= inc4; when inc4 => outregRd <= 1 ; regsel <= instrReg(2 downto 0); regWr <= 1 ; next_state <= incPc; when loadPc => progcntrRd <= 1 ; next_state <= loadPc2; when loadPc2 => progcntrRd <= 1 ; addrRegWr <= 1 ; next_state <= loadPc3; when loadPc3 => vma <= 1 ; rw <= 0 ; next_state <= loadPc4; when loadPc4 => vma <= 1 ; rw <= 0 ; if ready = 1 then instrWr <= 1 ; next_state <= execute; else next_state <= loadPc4; end if; when incPc => progcntrRd <= 1 ; alusel <= inc; shiftsel <= shftpass; next_state <= incPc2; when incPc2 =>

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